FIG. 1 is an illustration of a conventional four transistor (4T) pixel 100 and an associated load circuit 120. The pixel 100 includes a light sensitive element 101, shown as a photodiode, a floating diffusion node C, and four transistors: a transfer transistor 111, a reset transistor 112, a first source follower transistor 113, and a row select transistor 114. The pixel 100 accepts a TX control signal for controlling the conductivity of the transfer transistor 111, a RST control signal for controlling the conductivity of the reset transistor 112, and a ROW control signal for controlling the conductivity of the row select transistor 114. The voltage at the floating diffusion node C controls the conductivity of the first source follower transistor 113. The output of the source follow transistor is presented to the load circuit 120 through the row select transistor 114, which outputs a pixel signal at node B, when the row select transistor 114 is conducting.
The states of the transfer and reset transistors 111, 112 determine whether the floating diffusion node C is coupled to the light sensitive element 101 for receiving a photo generated charge as generated by the light sensitive element 101 during a charge integration period, or a source of pixel power VAAPIX at node A during a reset period.
The pixel 100 is operated as follows. The ROW control signal is asserted to cause the row select transistor 114 to conduct. At the same time, the RST control signal is asserted while the TX control signal is not asserted. This couples the floating diffusion node C to the pixel power VAAPIX at node A, and resets the voltage at node C to the pixel power VAAPIX. The pixel 100 outputs a reset signal Vrst to the load circuit 120. The load circuit 120 contains a load transistor 121, which is biased to a predetermined level VLN. Node B is coupled between the row select transistor 114 and the load transistor 121 and serves as an input to a sample and hold circuit which samples and holds the pixel reset voltage Vrst.
After the reset signal Vrst has been output, the RST control signal is deasserted. The light sensitive element 101 is exposed to incident light and accumulates charges on the level of the incident light during a charge integration period. After the charge integration period, the TX control signal is asserted. This couples the floating diffusion node C to the light sensitive element 101. Charge flows through the transfer transistor 111 and diminishes the voltage at the floating diffusion node C. The pixel 100 outputs a photo signal Vsig to the load circuit 120 which appears at node B and is sampled by the sample and hold circuit. The reset and photo signals Vrst, Vsig are different components of the overall pixel output (i.e., Voutput=Vrst−Vsig).
FIG. 2 is an illustration of an imager 200 that includes a plurality of pixels 100, 100′ forming a pixel array 201. The pixel array 201 includes an outer region 201a of barrier pixels 100′ and an inner region 201b of image pixels 100. Barrier pixels 100′ are similar to the image pixels 100, except they do not produce output signals that are processed by the imager. Barrier pixels 100′ improves the noise characteristics of the imager 200.
The imager 200 also includes row circuitry 210, column circuitry 220, an analog-to-digital converter 230, a digital processing circuit 240, and a storage device 250 for output. The imager 200 also includes a controller 260. The row circuitry 210 selects a row of pixels 100, 100′ from the pixel array 201. The pixels 100 in the selected row output their reset and pixel signals Vrst, Vsig to the column circuitry 220, which samples and holds the reset and pixel signals Vrst, Vsig. The column circuitry 220 also forms the pixel output (Vrst−Vsig), which is presented to the analog-to-digital converter 230 that converts the difference signal to a digital value. The digital value is then processed by the digital processing circuit 240, which stores the processed value in the storage device 250 for output. The controller 260 is coupled to the pixel array 201, row circuitry 210, column circuitry 220, digital processing circuit 240, and storage device 250, and provides control signals to perform the above described processing.
The pixel 100 is susceptible to a type of distortion known as eclipsing. That is, the pixel 100 outputs reset and photo signals Vrst, Vsig corresponding to a dark pixel when bright light is incident upon the pixel. Eclipsing can occur when very bright light is incident upon the pixel, which causes the light sensitive element 101 to produce a large amount of photogenerated charge. During the time when the pixel 100 is outputting the reset signal, the collected large charge at the light sensitive element 101 may spill over from the light sensitive element 101 to the floating diffusion node C, even when the transfer transistor 111 is off, which diminishes the voltage at node C. During the time when the pixel 100 is outputting a reset signal, the reverse biased PN junction at the floating diffusion node C also acts like a photodiode by collecting photo-generated excess carriers. This effect also diminishes the voltage at node C. The diminished voltage causes the pixel to output an incorrect (i.e., diminished voltage) reset signal Vrst; thereby causing the reset and photo signals Vrst, Vsig to be nearly the same voltage (for example, the photo and reset signals Vrst, Vsig may each be approximately 0 volts). The pixel output (Vrst−Vsig) therefore becomes approximately 0 volts, which corresponds to a voltage normally associated with a dark pixel.
FIG. 3 is an illustration of the pixel 100, its load circuit 120, and a proposed anti-eclipsing circuit 130 for overcoming this problem. The anti-eclipsing circuit 130 comprises a second source follower transistor 131 coupled in series with a switching transistor 132. The output of the switching transistor 132 is coupled in parallel with the output of the pixel 100 to the input of the load circuit 120 (i.e., to node B). The second source follower transistor 131 has one source/drain coupled to the pixel power VAAPIX. The second source follower transistor 131 is biased with a VREF control signal. The conductivity of the switching transistor 132 is controlled by a SHR control signal, which is the asserted when the column circuitry 220 (FIG. 2) of the imager 200 is sampling the reset signal Vrst from the pixel 100. The VREF voltage level is set so that if the voltage on the floating diffusion node C degrades while the reset signal Vrst is being output, the second source follower transistor 131 conducts and pulls the voltage at node B up to VREF minus the threshold voltage of the second source follower transistor 131. One key limitation of the anti-eclipsing circuit 130 relates to subthreshold conduction current flowing through the second source follower transistor 131. Even when anti-eclipsing is not needed, the subthreshold conduction current associated with the second source follower transistor 131 is output to node B as noise in the reset signal Vrst.
Accordingly, there is a need and desire for an improved anti-eclipsing circuit.